Logic devices such as field programmable gate arrays (FPGAs) are used to implement large systems that may include million of gates and megabits of embedded memory. The complexity of large systems often requires the use of electronic design automation (EDA) tools to create and optimize a design for the system onto physical target devices. Among the procedures performed by EDA tools in a computer aided design (CAD) flow are synthesis, placement, and routing.
The design for the system may include user logic created by an end user, one or more IP cores created by a third party vendor, or a combination of both. An IP core is a block of logic or data that is used to support one or more specific functionalities for the system. As essential elements of design reuse, IP cores are part of the growing EDA industry trend towards repeated use of previously designed components. Some IP cores have the characteristic of being entirely portable such that they may be inserted into any technology or design methodology. Universal Asynchronous Receiver/Transmitters (UARTs), central processing units, Peripheral Component Interconnect (PCI) interfaces, and double data rate (DDR) memory controllers are examples of some components with functionalities that may be implemented using IP cores.
Many types of IP cores that implement standardized functions on target devices are delivered by FPGA vendors and their partners. In many cases, it is difficult to implement the IP core such that the performance of the IP core meets the standard's specification. Typically a target device vendor produces a compiled version of the IP core that is fully placed and routed on a target device. This implementation is analyzed to ensure that it meets a required performance that may be specified by the standard. The target device vendor delivers to the end customer the compiled version of the IP core, including the information needed for the customer to produce the exact placement and routing required to meet the required performance.